Image signals are subjected to various kinds of processing in accordance with the specification of an apparatus which performs image display or the like. For example, in displaying analog images, image signals are sampled with a sampling clock having the same cycle as the clock of the input image signals. FIG. 7 is a configuration diagram of a circuit for displaying images. As shown in FIG. 7, a TFT (Thin Film Transistor) liquid crystal display 105 displays image signals from an image output circuit section 102 which generates and outputs various images, such as navigation images. The TFT liquid crystal display 105 samples image signals on the basis of a sampling clock from a display timing circuit section 103 and performs drawing processing. The display timing circuit section 103 generates the sampling clock in synchronization with a horizontal synchronization signal from the image output circuit section 102 on the basis of signals oscillated by an oscillation circuit section 106.
FIGS. 8 and 9 are timing charts showing the relationship between the clock of the input image signals and the sampling clock. As shown in FIG. 8, when the clock of the input image signals coincides with the sampling clock, in the TFT liquid crystal display 105, the image signals are correctly sampled, such that the images are appropriately displayed. Meanwhile, as shown in FIG. 9, when the clock of the input image signals does not coincide with the sampling clock, in the TFT liquid crystal display 105, the image signals are not correctly sampled, such that the images are inappropriately displayed. In this case, blotting or profile blurring occurs in the displayed characters.
PTL 1 describes an image display device which changes the division ratio of a divider in a PLL (Phase-Locked Loop) circuit. PTL 2 describes a clock generating circuit which partially masks a sampling clock to carry out frequency conversion with a simple configuration.